Ensuring the correctness of electronic designs is critical, as hardware flaws are permanent post-production and can compromise software reliability or the safety of cyber-physical systems. Verification is central to digital circuit engineering, with FPGA and IC/ASIC projects dedicating 40% and 60% of their time, respectively, to this process. While testing approaches, such as directed or constrained random testing, are easy to implement, they are inherently non-exhaustive and cannot ensure the absence of critical errors. Formal verification, particularly model checking, addresses these limitations by mathematically confirming whether a design satisfies its specifications across all possible executions. However, methods like BDDs and SAT solvers remain computationally intensive and struggle to scale for complex circuits. Engineers often rely on bounded model checking to reduce computational demands, which sacrifices global correctness over extended time horizons.
Formal verification has evolved over decades, with temporal logic playing a key role in describing system behaviors. Based on Linear Temporal Logic (LTL), SystemVerilog Assertions are widely used to define safety and liveness properties. Safety properties are efficiently verified using BDDs, while SAT-based methods scale better for bounded model checking but remain incomplete without achieving impractically high thresholds. Advanced techniques like IC3 and Craig Interpolation improve unbounded safety checking, while Emerson-Lei fixed-point computations and k-liveness extend verification to liveness properties. Verifying systems with complex arithmetic remains challenging, often requiring explicit-state abstractions, inductive invariants, or ranking functions. Originally developed for software termination analysis, ranking functions have been generalized for hardware liveness verification, incorporating non-linear, piecewise-defined, and lexicographic methods to address modern system complexities.
Researchers from the University of Birmingham, Amazon Web Services, and Queen Mary University of London have developed a machine learning-based approach for hardware model checking that integrates neural networks and symbolic reasoning. Their method uses neural networks to represent proof certificates for LTL specifications, trained from randomly generated system executions. The approach guarantees formal correctness over unbounded time horizons by employing satisfiability solving to validate these certificates. Experiments demonstrate its effectiveness, outperforming both academic and commercial model checkers in speed and task completion across standard hardware verification problems, contributing to improved safety and reliability in system designs.
LTL model checking verifies if all possible sequences of actions in a system (M) comply with a given LTL formula (Phi), which describes the desired temporal properties. The system (M) includes input and state variables, with its behavior determined by transition rules. To check this, (Phi) is converted into a type of automaton called a Büchi automaton (A_Phi). The verification ensures that the combined system (M) and the automaton (A_neg Phi) (representing the formula’s negation) have no valid infinite sequences. Neural ranking functions aid in proving termination and are validated using SMT solvers.
The experimental evaluation tested 194 verification tasks derived from 10 parameterized hardware designs with varying complexity. A prototype neural model-checking tool was developed, using Spot to generate automata, Verilator for data generation, PyTorch for training, and Bitwuzla for SMT-solving. The tool was benchmarked against industry leaders ABC, nuXmv, and anonymized tools X and Y. It completed 93% of tasks, outperforming competitors in scalability and runtime, although challenges like local minima and extended SMT-check times remain. While generally faster, it struggled with trivial tasks like UARTt due to overhead. The method’s limitations include reliance on word-level inputs and risks of dataset bias.
In conclusion, the study introduces an approach to model-checking temporal logic using neural networks as proof certificates for hardware verification. Neural networks are trained on synthetic system executions, leveraging their ability to represent ranking functions for fair termination. The method combines machine learning and symbolic reasoning by validating neural certificates with satisfiability solvers, ensuring formal guarantees. Applied to SystemVerilog designs, it outperforms state-of-the-art tools in scalability. Despite the computational demand of SMT solving, the approach is effective with simple feed-forward networks. This marks the first successful use of neural certificates for temporal logic, establishing a foundation for further advancements in model checking.
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